Education

• Ph.D., Computer Science, University of California at Los Angeles (1998). Major field of study: VLSI CAD. Minor fields of study: Computer Architecture, Programming Languages and Systems.
• M.S., Computer Science, New Mexico Institute of Mining and Technology (1989)
• B.S., Computer Science and Mathematics, New Mexico Institute of Mining and Technology (1987)

Employment

• Associate Professor, State University of New York at Binghamton, 2004-present.
• Visiting Professor, University of Kitakyushu, 2004-2005.
• Assistant Professor, State University of New York at Binghamton, 1998-2004.

Research

• Director, BLAC CAD Group, SUNY Binghamton.  Research focus on fast placement for large circuits, novel VLSI routing architectures, and new Steiner tree formulations.
• Research Assistant, UCLA Computer Aided Design Lab, Prof. Jason Cong, Ph.D., advisor (1992 to 1998).  Performed research on fundamental problems in the VLSI CAD field, with an emphasis on high performance interconnect design, system level performance optimization, and novel approaches to routing and placement.
• Research Assistant, New Mexico Institute of Mining and Technology, Prof. Wen-Ben Jone, Ph.D., advisor (1989). Performed research on the construction of test sets for circuit verification.

• C. Li, M. Xie, C.-K. Koh, J. Cong, and P. H. Madden, “Routability-Driven Placement and White Space Allocation,” IEEE Trans. Computer-Aided Design, Vol. 26, No. 5, May 2007, pp. 858-871.
• P. H. Madden, “Forty Years of Amdahl’s Law (workshop paper),” EDPS 2007.
• A. R. Agnihotri and P. H. Madden, “Fast Analytic Placement using Minimum Cost Flow,” in Proc. ASPDAC 2007, pp. 128-134.
• S. Ono, S. Tilak, and P. H. Madden, “Bisection Based Placement for the X Architecture,” in Proc. ASPDAC 2007, pp. 153-158.
• A. R. Agnihotri and P. H. Madden, “Legalization and Detailed Placement (book chapter)” in “The Handbook of Algorithms for VLSI Physical Design Automation,” C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, editors. To appear, 2007.
• A. R. Agnihotri, S. Ono, and P. H. Madden, “Placement for Power Optimization (book chapter), in “Closing the POWER Gap between ASIC & Custom,” D. Chinnery and K. Keutzer, editors. To appear, 2007.
• A. R. Agnihotri, S. Ono, M. C. Yildiz, and P. H. Madden, “Large Scale Circuit Placement (book chapter),” in “High-Performance Energy-Efficient Microprocessor Design,” V. G. Oklobdzija and R. K. Krishnamurthy, editors. 2006.
• M. C. Bell and P. H. Madden, “On the Marketing of Multicore (workshop paper),” in EDPS 2006.
• P. Agarwal, A. Vidyarthi, and P. H. Madden, "Performance Analysis by Topology Indexed Lookup Tables," pp. 3579-3582, ISCAS05.
• A. R. Agnihotri, S. Ono, C. Li, M. C. Yildiz, A. Khatkhate, C.-K. Koh, and P. H. Madden, "Mixed Block Placement via Fractional Cut Recursive Bisection," IEEE Trans. on Computer-Aided Design, Vol 24, No. 5, pages 748-761, May 2005.
• P. H. Madden, "SuperSized VLSI: A Recipe for Disaster," EDP, April 2005.
• J. Westra, P. Groeneveld, T. Yan, and P. H. Madden, "Global Routing: Metrics, Benchmarks, and Tools," EDP, April 2005.
• A. R. Agnihotri, S. Ono, and P. H. Madden, "Recursive Bisection Placement: Feng Shui 5.0 Implementation Details", ISPD2005, pp. 230-232, April 2005.
• P. Ramachandaran, A. R. Agnihotri, S. Ono, P. Damodaran, K. Srihari, and P. H. Madden, "Optimal Placement by Branch-and-Price," pp. 337--341, ASPDAC05.
• C. Li, C.-K. Koh, and P. H. Madden, "Floorplan Management: Incremental Placement for Gate Sizing and Buffer Insertion," pp. 349--354, ASPDAC05.
• S. Ono and P. H. Madden, "On Structure and Suboptimality in Placement," pp. 331--336, ASPDAC05.
• C. Li, M. Xie, C.-K. Koh, J. Cong, and P. H. Madden, "Routability-Driven Placement and White Space Allocation," in ICCAD04.
• S. Pujari, R. M. Smey, T. Yan, H. H. Madden, and P. H. Madden, "Interconnect Synthesis for Lithography and Manufacturability in Deep Submicron Design," in SASIMI04.
• S. Ono and P. H. Madden, "Clusters First? A Study of Circuit Structure and Placement" in MWSCAS04.
• S. Adya, M. C. Yildiz, I. L. Markov, P. G. Villarrubia, P. N. Parakh, and P. H. Madden, "Benchmarking for Large-Scale Placement and Beyond," IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, 23(4), April 2004.
• A. Khatkhate, C. Li, A. R. Agnihotri, M. C. Yildiz, S. Ono, C.-K. Koh, and P. H. Madden, "Recursive Bisection Based Mixed Block Placement," in Proc. International Symposium on Physical Design, April 2004.
• A. R. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and P. H. Madden, "Fractional Cut: Improved Recursive Bisection Based Placement," in Proc. ICCAD 2003.
• R. Hadsell and P. H. Madden, "Improved Global Routing by Amplified Congestion Estimation," Design Automation Conference, June 2003, pp. 28--34.
• A. Agnihotri and P. H. Madden, "Congestion Reduction in Traditional and New Routing Architectures," Great Lakes Symposium on VLSI, April 2003, pp. 211--214.
• S. N. Adya, I. L. Markov, P. G. Villarrubia, P. Parakh, M. C. Yildiz, and P. H. Madden, "Benchmarking for Large-Scale Placement and Beyond,", International Symposium on Physical Design, April 2003, pp. 95--.
• R. M. Smey, W. Swartz, and P. H. Madden, "Crosstalk Minimization during Detail Routing," Design Automation and Test Europe, March 2003, pp. 862--
• M. C. Yildiz and P. H. Madden, "Preferred Direction Steiner Trees," IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, 21(11), November 2002, pp. 1368--1372.
• P. H. Madden, "Reporting of Standard Cell Placement Results," IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, 21(2), February 2002, pp. 240--247.
• J. Cong, C.-K. Koh, and P. H. Madden, "Interconnect Layout Optimization Under Higher-Order RLC Model for MCM Designs," IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, 20(12), December 2001, pp. 1455--1463.
• F. Khundakjie, N. B. Abu-Ghazaleh, M. C. Yildiz and P. H. Madden, "Parallel VLSI Standard Cell Placement on a Cluster of Workstations," Proc. IEEE Clusters, October 2001, pp. 529-553.
• M. C. Yildiz and P. H. Madden, "Improved Cut Sequences for Partitioning Based Placement", Proc. Design Automation Conference, 2001, pp. 776--779.
• P. H. Madden, "Reporting of Standard Cell Placement Results, Proc. Int'l Symp. on Physical Design, 2001, pp. 30--35.
• M. C. Yildiz and P. H. Madden, "Preferred Direction Steiner Trees", GLSVLSI2001, 2001, pp. 56--61.
• M. C. Yildiz and P. H. Madden, "Global Objectives for Standard Cell Placement", GLSVLSI2001, 2001, pp. 68--72.
• N. Ternullo, N. Mehravari, R. J. Szczerba, and P. H. Madden, "InfoFlo: A Novel Communications Infrastructure for PDAs," Proc. IEEE SMC, 2000.
• C.-K. Koh and P. H. Madden, "Manhattan or non-Manhattan? A Study of Alternative VLSI Routing Architectures", GLSVLSI 2000.
• P. H. Madden, "Partitioning by Iterative Deletion", Proc. Int'l Symp. on Physical Design, 1999, pp. 83--89.
• P. H. Madden, "High Performance VLSI Global Routing", UCLA PhD dissertation, 1998.
• J. Cong and P. H. Madden, "Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs," Proc. Design Automation Conference, 1998, pp. 356-361.
• J. Cong and P. H. Madden, "Performance Driven Routing with Multiple Sources", IEEE Trans. Computer-Aided Design, V. 16, No. 4, April 1997, pp. 410-419.
• J. Cong and P. H. Madden, "Performance Driven Global Routing for Standard Cell Design", Proc. Int'l Symp. on Physical Design, Napa, California, April 1997, pp. 73-80.
• J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance Optimization of VLSI Interconnect Layout" Integration, J. 21, 1996, pp. 1-94.
• J. Cong and P. H. Madden, "Performance Driven Routing with Multiple Sources", Proc. Int'l Symp. on Circuits and Systems, Seattle, Washington, May 1995, pp. 1.203--1.206.
• W.-B. Jone and P. H. Madden, "Multiple-Fault Testing Using Single Fault Test Set for Fanout-Free Circuits", IEEE Trans. Computer-Aided Design, V. 12, No. 1, January 1993, pp. 149-158.

• IBM Faculty Award 2002, on Next Generation VLSI Physical Design.
• NSF, "Functionality Based Area Routing," with matching funds from New York State.
• SRC/IBM, multiple voltage placement, with matching funds from IEEC.
• Microelectronics Design Center (a NYSTAR supported research center), next generation physical design tools.
• Sun Microsystems grant for access to their Grid.
• Equipment grant from Intel.

• Member, ACM, IEEE.  Vice-Chair, ACM/SIGDA.
• Associate Editor, IEEE Transactions on Computer Aided Design.
• General chair, ISPD2007; Steering Committee chair, ISPD2008.
• General Chair, EDP 2008.
• Co-chair, GLSVLSI2002.
• Technical program and best paper committees for various conferences, including ISPD, ASPDAC, ICCAD, GLVLSI, EDP.

Patents

• N. J. Ternullo, N. Mehravari, and P. H. Madden, "7,280,823: Method and apparatus for determining the context of a handheld device."
• N. J. Ternullo, N. Mehravari, and P. H. Madden, “7,215,887, Method and apparatus for infrared data communication.”
• N. J. Ternullo, N. Mehravari, and P. H. Madden, "6,954,893, Method and apparatus for reliable unidirectional communication in a data network."
• Four patent applications currently pending.